Multi-temperature trimming of an integrated circuit (IC) device at wafer test, final test, or in the field application can be achieved by using an integrated (on-chip) heater to introduce a temperature rise over a specific area of the substrate (e.g., silicon). For example, one IC device that may be trimmed comprises a precision analog device, such as voltage reference or analog to digital converter (ADC), which comprises both passive devices (resistors, capacitors) and active devices (e.g., transistors) configured to provide the desired circuit function.
However, with known multi-temperature parametric trimming methods, the temperature both across the heated region above the substrate (e.g., thin film resistors or polysilicon resistors within a dielectric) and in the heated region within the substrate (e.g., transistors or diffused resistors on silicon) below can both have a significantly non-uniform temperature distribution. Moreover, there can be a significant temperature differential between the heated region above the substrate where the thin film resistors or polysilicon resistors reside and in the substrate where active devices (e.g., transistors) and passive devices (e.g., diffused resistors) reside. When trimming the IC device to minimize its temperature dependence, non-uniform temperature distributions introduce trimming errors, preventing the IC from being trimmed to a more optimal operating point, thus limiting the obtainable level of precision of the IC device.